Non-Volatile Memory Device and Method for Manufacturing the Same

ABSTRACT

An increase of charge storing capacity, prevention of an over-erase, and a reduction of ΔVth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than the gate, a pair of storage layers at the lateral sides of the gate, a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers, a source and a drain formed in the semiconductor substrate at first opposed locations external to the gate, and a trap impurity implanted into the insulating layer at second locations external to the gate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of copending U.S. patentapplication Ser. No. 11/205,542, filed on Aug. 16, 2005 (Attorney DocketNo. OPP-GZ-2007-0248-US-00), which is incorporated herein by referencein its entirety, and which claims priority to and the benefit of KoreanPatent Application No. 10-2004-0064416 filed in the Korean IntellectualProperty Office on Aug. 16, 2004, the entire contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a non-volatile memory device and amethod for manufacturing the same. More particularly, the presentinvention relates to a non-volatile memory device providing two bits percell and having an enhanced programming capacity and efficiency, and amethod for manufacturing the same.

(b) Description of the Related Art

In a non-volatile memory device (among various semiconductor memorydevices), data are not erased even when power is turned off.

At present, the non-volatile memory devices are divided into floatinggate memory devices, and MIS (metal-insulator-semiconductor) memorydevices in which two or more kinds of dielectric layers are stacked toform a double layer or a triple layer.

The floating gate non-volatile memory devices realize their memorycharacteristic using a potential well. The MIS non-volatile memorydevices realize their memory characteristic using a trap existing in aninterface (e.g., a charge trapping or charge storage capability providedby certain materials and/or the interface between them).

For a MIS non-volatile memory device, asilicon-oxide-nitride-oxide-semiconductor (SONOS) structure is widelyadopted.

A typical structure of a conventional planar type SONOS device isillustrated in FIG. 1.

As shown in FIG. 1, according to a conventional SONOS device, a firstoxide layer 2, a nitride layer 3, and a second oxide layer 4 are stackedon a semiconductor substrate 1 in an oxide-nitride-oxide (ONO) structure5, and a gate 6 is formed thereabove. A source 7 and a drain 8 areformed in the semiconductor substrate 1 at positions or locationshorizontally external to the gate 6.

An advance to such a conventional SONOS structure concerns a 2-bit/cellstructure providing two bits per cell, introduced to increase memorycapacity with the same gate width.

FIG. 2 is a cross-sectional view of a conventional SONOS device in a2-bit/cell structure. As shown in FIG. 2, a gate 12 is formed above asemiconductor substrate 10, and a first oxide layer 11 is formed betweenthe gate 12 and the semiconductor substrate 10 and at each lateral sideof the gate 12.

A nitride layer 13 is formed lateral to the first oxide layer 11 (thatwas formed laterally to the gate 12). The gate 12 is further providedwith a second oxide layer 14 that covers the nitride layer 13. A source15 and a drain 16 are formed in the semiconductor substrate 10 atpositions horizontally external to the gate 12.

However, charges may not be effectively trapped under all circumstancesin such a 2-bit/cell structure since an area for trapping the charges issmall.

Furthermore, when the first oxide layer is degraded, charges may escapeto the substrate while storing programmed data. In this case, athreshold voltage Vth of the transistor device may be lowered, and thusa ΔVth may decrease. Here, the ΔVth denotes a voltage difference betweenthreshold voltages Vth in a forward bias and a reverse bias. A reductionof ΔVth level may cause a problem of an over-erase, and therefore, theΔVth is recommended to remain as constant as possible.

The above information disclosed in this Background section is only forenhancement of understanding of the background of the invention, andtherefore, it may contain information that does not form prior art thatmay be already known in this or another country to a person of ordinaryskill in the art.

SUMMARY OF THE INVENTION

An exemplary non-volatile memory device according to an embodiment ofthe present invention includes a gate of a predetermined width above asemiconductor substrate, an insulating layer between the gate and thesemiconductor substrate and at lateral sides of the gate, having agreater width than that of the gate, a pair of storage layers at thelateral sides of the gate, a pair of blocking layers at the lateralsides of the gate and covering the pair of storage layers, a source anda drain in the semiconductor substrate at opposite locations external tothe gate, and a trap impurity implanted into the insulating layer atsecond locations external to the gate.

The trap impurity may be near an interface of the semiconductorsubstrate with the insulating layer, and may comprise nitrogen,germanium, and/or oxygen.

The insulating layer and the blocking layer may each respectivelycomprise an oxide layer, and the storage layer may comprise a nitridelayer.

An exemplary method for manufacturing a non-volatile memory deviceaccording to an exemplary embodiment of the present invention includesforming a bottom insulating layer on a semiconductor substrate, forminga gate of a predetermined width on the bottom insulating layer, forminga side wall insulating layer on the gate, implanting a trap impurityinto the bottom insulating layer at locations external to the gate,forming a pair of storage layers at lateral sides of the gate, forming asource and a drain in the semiconductor substrate at opposite locationsexternal to the pair of storage layers by ion implantation, and forminga pair of blocking layers at opposite sides of the gate and covering thepair of storage layers.

Implanting the trap impurity may comprise implanting near an interfaceof the semiconductor substrate with the bottom insulating layer. Thetrap impurity may be implanted by a thermal diffusion method or a methodusing plasma.

Implanting the trap impurity may comprise implanting nitrogen at atemperature of 700-900° C. from NO and/or N₂ gas, and nitrogen may beimplanted from N₂ gas in or under an Ar or He plasma atmosphere.

Forming the pair of storage layers may include forming a storage layermaterial above the semiconductor substrate, and anisotropically etchingthe storage layer material above the semiconductor substrate so as toform (or leave) the pair of storage layers on the lateral sides of thegate. Such anisotropic etching of the storage layer material maycomprise etching the storage layer material until a height of thestorage layer becomes lower than that of the gate.

Forming the pair of blocking layers may include forming a blocking layermaterial above the semiconductor substrate, and anisotropically etchingthe blocking layer material so as to form (or leave) the pair ofblocking layers on lateral sides of the gate. Anisotropically etchingthe blocking layer material may comprise etching the blocking layermaterial until the gate is exposed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional planar type SONOSdevice.

FIG. 2 is a cross-sectional view of a conventional SONOS device in a2-bit/cell structure.

FIG. 3A to 3C are cross-sectional views showing sequential stages of amethod for manufacturing a non-volatile memory device according to anexemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

An embodiment of the present invention will hereinafter be described indetail with reference to the accompanying drawings.

FIG. 3A to 3C are cross-sectional views showing sequential stages of amethod for manufacturing a non-volatile memory device according to anexemplary embodiment of the present invention, among which FIG. 3Cillustrates a non-volatile memory device according to an exemplaryembodiment of the present invention.

As shown in FIG. 3C, a non-volatile memory device according to anexemplary embodiment of the present invention includes a gate 120 of apredetermined width formed above a semiconductor substrate 100.

Further, an insulating layer 110 is between the gate 120 and thesemiconductor substrate 100 and at lateral sides of the gate 120. Here,a width of the insulating layer 110 on the semiconductor substrate 100may be greater than a width of the gate 120, such that the insulatinglayer 110 protrudes or extends along both lateral directions external tothe gate 120.

A storage layer 130, e.g., comprising nitride (such as silicon nitride),is formed at opposed lateral sides of the gate 120. That is, a pair ofstorage layers 130 are formed for each gate 120.

A blocking layer 160 is formed on each storage layer 130. That is, apair of blocking layers 160 are positioned at opposed lateral sides ofthe gate 120, respectively covering the pair of storage layers 130.Typically, gate 120 separates the individual storage layers 130 andblocking layers 160, and an upper surface of gate 120 is exposed beforeany further materials (other than the corresponding storage layermaterial and blocking layer material) are subsequently depositedthereon.

A source 140 and a drain 150 are formed in the semiconductor substrate100 at locations horizontally external to opposed sidewalls of the gate120. Optionally, the locations of source 140 and drain 150 aresubstantially aligned with or external to the outer sidewalls of storagelayers 130.

A trap impurity 200 such as nitrogen is implanted in the insulatinglayer 110 at locations horizontally external to the gate 120. The trapimpurity 200 breaks bonds of atoms in the insulating layer 110 (that is,it breaks a crystal structure of the insulating layer 110), and trapsites are formed at such positions of broken crystal structure.Therefore, any atoms can be used as the trap impurity 200 if, whenimplanted into the insulating layer 110, they form a trap site (whichmay be chemically more unstable than the non-implanted insulating layer110, due to the implanted impurity atoms breaking the crystal structureof the insulating layer 110). Generally, the implanted atoms causenegligible damage to the insulating layer 110, such that insulatingcharacteristics of the insulating layer 110 are not destroyed or badlyaffected, and preferably, at least in part, they do not form a stablecompound by reacting with the insulating layer 110. For example,nitrogen, germanium, oxygen, combinations thereof, etc. may be used asthe trap impurity 200.

In addition, it is preferable that the trap impurity 200 is deeplyimplanted such that it is also near to an interface of the semiconductorsubstrate 100 and the insulating layer 110 (i.e., close to thesemiconductor substrate 100), as opposed to only at or near an externalsurface of the insulating layer 110.

The non-volatile memory device becomes a so-called SONOS device when thesemiconductor substrate 100 and the gate 120 comprise silicon, theinsulating layer 110 and the blocking layer 160 comprise oxide layers,and the storage layer 130 comprises a nitride layer.

Concentration of the trap impurity 200 may vary, depending on the typeand/or design of the device to be manufactured. For example, for a SONOSdevice, nitrogen may be implanted at a concentration of about 10²²atoms/cm³.

Hereinafter, a method for manufacturing a non-volatile memory deviceaccording to an exemplary embodiment of the present invention will bedescribed in detail.

As shown in FIG. 3A, a bottom insulating layer 110 a of an insulatingmaterial such as an oxide (e.g., undoped silicon dioxide) is firstlyformed on the semiconductor substrate 100 (generally by wet or drythermal oxidation, but alternatively, by chemical vapor deposition), andthen a gate 120 is formed at a predetermined width on the bottominsulating layer 110 a (generally by deposition of an amorphous siliconlayer, which is then crystallized [generally by annealing], patterned byconventional photolithography, and etched by conventional wet or dryetching of polycrystalline silicon).

Subsequently, a side wall insulating layer 110 b of an insulatingmaterial such as an oxide (e.g., undoped silicon dioxide or a siliconoxide doped with fluorine or with boron and/or phosphorous) is formed onthe gate 120. When insulating layer 110 b comprises or consistsessentially of undoped silicon dioxide, it is generally formed by wet ordry thermal oxidation. However, when insulating layer 110 b comprises orconsists essentially of a doped silicon oxide, it may be formed by aconventional chemical vapor deposition process. According to anexemplary embodiment of the present invention, the side wall insulatinglayer 110 b and the bottom insulating layer 110 a comprise the samematerial (e.g., undoped silicon dioxide, formed by wet or dry thermaloxidation). In this case, they are generally not differentiable, andhereinafter they are collectively called an insulating layer 110.

Subsequently, as shown in FIG. 3B, the trap impurity 200 is implantedinto the insulating layer 110 at locations external to the gate 120.Nitrogen, germanium, oxygen, etc. may be implanted as the trap impurity200. The trap impurity 200 may be implanted by a thermal diffusionmethod or a method using plasma.

In more detail, nitrogen may be implanted at a temperature of 700-900°C. from an NO gas, or it may be implanted from, in or under an Ar or Heplasma atmosphere further containing an N₂ gas.

As described above, it is preferable that the trap impurity 200 isdeeply implanted, such that it is also close to an interface of thesemiconductor substrate 100 with the insulating layer 110 (i.e., near tothe semiconductor substrate 100), rather than only near to or at anexternal or upper surface of the insulating layer 110. Using knownimplantation techniques, one may implant an impurity such that itsconcentration maximum is closer to the semiconductor substrate100-insulating layer 110 interface than to the upper surface of theinsulating layer 110.

According to the thermal diffusion method, it is easy to deeply implantthe trap impurity 200 such that its concentration maximum is closer tothe interface with the substrate 100 than to the surface of theinsulating layer 110. However, the thermal diffusion method has adrawback in that the impurity concentration cannot be preciselycontrolled. On the other hand, using a plasma method, the trap impurityconcentration can be controlled to a desired level, and thus the methodusing plasma is more accepted.

Other process conditions, such as a chamber pressure, for implanting thetrap impurity 200 may be set depending on the implantation apparatusused.

Subsequently as shown in FIG. 3C, a storage layer 130, such as a nitride(e.g., silicon nitride) layer, is formed on each opposed, lateral sideof the gate 120. In more detail, the material for storage layer 130 maybe deposited on the entire semiconductor substrate 100, and then thestorage layer material may be anisotropically etched to leave the pairof storage layers 130 at the lateral sides of the gate 120. In thiscase, the storage layer material is anisotropically etched until aheight of the storage layer 130 becomes smaller than that of the gate120.

Subsequently, the source 140 and the drain 150 are formed by ionimplantation in the semiconductor substrate 100 at opposite locationsexternal to the gate 120 and the storage layer 130. Thus, the source 140and drain 150 may be substantially aligned with external sidewalls ofthe two storage layers 130.

Then, a blocking layer 160 is formed at each side external to the gate120 such that it may cover the storage layer 130. In more detail, thematerial for blocking layer 160 may be deposited on the entiresemiconductor substrate 100, and then the blocking layer material may beanisotropically etched to leave the pair of blocking layers 160 at thelateral sides of the gate 120, covering the two storage layers 130. Inthis case, the blocking layer 160 is anisotropically etched until thegate 120 is exposed.

According to the above described process, a non-volatile memory deviceaccording to an exemplary embodiment is manufactured.

As described above, according to an exemplary embodiment of the presentinvention, trap sites are formed in an insulating layer under a storagelayer by implanting a trap impurity (e.g., impurity atoms that may notcompletely react with the insulating layer material to form stablecompounds). Therefore, charge carriers (e.g., electrons and/or holes)may easily flow into the storage layer through the trap sites, and thus,storing and/or erasing data may become easier. Further, the storagecapacity and storage efficiency of a non-volatile memory device may beincreased.

In addition, the trap sites may prevent reduction or escape of thecharges from the storage layer back to the semiconductor substrate.Therefore, the present invention may reduce or prevent an over-erasecondition, an increase of ΔVth, and/or degradation of the insulatinglayer.

While this invention has been described in connection with what ispresently considered to be practical exemplary embodiments, it is to beunderstood that the invention is not limited to the disclosedembodiments, but, on the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

1. A non-volatile memory device, comprising: a gate of a predeterminedwidth above a semiconductor substrate; an insulating layer between thegate and the semiconductor substrate and at lateral sides of the gate,having a greater width than that of the gate; a pair of storage layersat lateral sides of the gate; a pair of blocking layers at the lateralsides of the gate and covering the pair of storage layers; a source anda drain in the semiconductor substrate at first locations external tothe gate; and a trap impurity in the insulating layer at secondlocations external to the gate.
 2. The non-volatile memory device ofclaim 1, wherein the trap impurity is near an interface of thesemiconductor substrate with the insulating layer.
 3. The non-volatilememory device of claim 2, wherein the trap impurity has a maximumconcentration closer to the interface of the semiconductor substratewith the insulating layer than to an upper surface of the insulatinglayer.
 4. The non-volatile memory device of claim 1, wherein the trapimpurity comprises nitrogen, germanium, and/or oxygen.
 5. Thenon-volatile memory device of claim 4, wherein the trap impuritycomprises a combination of nitrogen, germanium, and/or oxygen.
 6. Thenon-volatile memory device of claim 4, wherein the insulating layer andthe blocking layer each independently comprise an oxide layer, and thestorage layer comprises a nitride.
 7. The non-volatile memory device ofclaim 6, wherein the trap impurity comprises nitrogen, the nitrogenhaving a concentration of about 10²² atoms/cm³.
 8. The non-volatilememory device of claim 1, wherein the insulating layer and the blockinglayer each independently comprise an oxide layer, and the storage layercomprises a nitride.
 9. The non-volatile memory device of claim 8,wherein the storage layer comprises silicon nitride.
 10. Thenon-volatile memory device of claim 1, wherein each of the storagelayers is capable of independently storing a bit of data.
 11. Thenon-volatile memory device of claim 1, wherein the source and drain aresubstantially aligned with external sidewalls of the pair of storagelayers.
 12. The non-volatile memory device of claim 1, wherein theinsulating layer comprises a bottom insulating layer.
 13. Thenon-volatile memory device of claim 12, wherein the bottom insulatinglayer comprises an oxide.
 14. The non-volatile memory device of claim 1,further comprising a side wall insulating layer on the gate.
 15. Thenon-volatile memory device of claim 14, wherein the side wall insulatinglayer comprises an oxide.
 16. The non-volatile memory device of claim15, wherein the side wall insulating layer comprises silicon oxide dopedwith fluorine, boron, and/or phosphorous.
 17. The non-volatile memorydevice of claim 15, wherein the side wall insulating layer comprisesundoped silicon oxide.
 18. The non-volatile memory device of claim 1,wherein the device comprises trap sites, the trap sites having the trapimpurity.
 19. The non-volatile memory device of claim 1, wherein aheight of the storage layer is less than a height of the gate.
 20. Thenon-volatile memory device of claim 1, wherein the device is a SONOSdevice.